Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology

Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology

a low-power and low-energy 1-bit full adder cell using 32nm cnfet technology node

full adder cell is often placed in the critical path of other circuits. therefore it plays an important role in determining the entire performance of digital system. moreover, portable electronic systems rely on battery and low-power design is another concern. in conclusion it is a vital task to design high-performance and low-power full adder cells. since delay opposes against power consumptio...

A Novel High-speed Adder-Subtractor Design based on CNFET

Carbon Nanotube filed-effect transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometrydependent threshold voltage is one of the CNFET characteristics, which is used in the proposed design. In this paper, we present a novel high speed Adder-subtractor cell using CNFETs based on XOR gates and multiplexer. Presented design uses fourteen transistors, ten for full ...

Symmetrical, Low-Power, and High-Speed 1-Bit Full Adder Cells Using 32nm Carbon Nanotube Field-effect Transistors Technology (TECHNICAL NOTE)

Carbon nanotube field-effect transistors (CNFETs) are a promising candidate to replace conventional metal oxide field-effect transistors (MOSFETs) in the time to come. They have considerable characteristics such as low power consumption and high switching speed. Full adder cell is the main part of the most digital systems as it is building block of subtracter, multiplier, compressor, and other ...

Energy Efficient 1-Bit Full Adder Cells for Low Voltage

We present eight new designs for 1-bit full adder cell featuring hybrid CMOS logic style. These designs are based on a novel XOR-XNOR circuit that simultaneously produces XOR and XNOR full-swing outputs and outperforms its best counterpart showing 39% improvement in PDP. The new full-adder designs are also categorized in three main categories depending upon the implementation of the logic expre...